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Title:Simulator logičnih vrat : zaključno delo
Authors:ID Zakošek, Sandi (Author)
ID Mongus, Domen (Mentor) More about this mentor... New window
ID Bizjak, Marko (Co-mentor)
Files:.pdf VS_Zakosek_Sandi_2019.pdf (836,20 KB)
MD5: 89B24AEF23FF222F4E80D674A0EA29FF
 
Language:Slovenian
Work type:Bachelor thesis/paper (mb11)
Typology:2.11 - Undergraduate Thesis
Organization:FERI - Faculty of Electrical Engineering and Computer Science
Abstract:Zaradi pomembnosti logičnih vezij dandanes obstaja veliko različnih spletnih in namiznih aplikacij (na primer simulator.io, Logicly, The Logic Lab), ki nam omogočajo simuliranje njihovega delovanja. Večina obstoječih simulatorjev je osnovanih tako, da na osnovi izbranih vhodnih vrednosti simulirajo izhode izbranega logičnega vezja. Čeprav je to razumljivo, saj se lahko več vhodov v logično vezje preslika v enak izhod, zgolj enosmerna simulacija omejuje možnosti obratnega inženirstva. V diplomskem delu naslovimo ta izziv, z razvojem algoritma, ki je zmožen analizirati izbrano logično vezje in ob podanih izhodnih vrednostih ovrednotiti pravilne vhodne vrednosti. Izdelan simulator omogoča izbor logičnih vrat in sekvenčnih vezij, na osnovi tega pa ovrednoti vhodne vrednosti za želen rezultat na izhodu. Pravilnost delovanja simulatorja smo preverili s kombiniranjem izbir, pri čemer smo ovrednotili tudi hitrost delovanja.
Keywords:Logična vrata, sekvenčno vezje, obratno inženirstvo, logične funkcije, algoritema
Year of publishing:2019
Place of performance:Maribor
Publisher:[S. Zakošek]
Number of pages:VIII, 42 str.
Source:Maribor
UDC:004.94:004.312.22(043.2)
COBISS.SI-ID:22577686 New window
NUK URN:URN:SI:UM:DK:NJ2Q2B7U
Publication date in DKUM:04.09.2019
Views:1255
Downloads:122
Metadata:XML RDF-CHPDL DC-XML DC-RDF
Categories:KTFMB - FERI
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Licences

License:CC BY-NC-ND 4.0, Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International
Link:http://creativecommons.org/licenses/by-nc-nd/4.0/
Description:The most restrictive Creative Commons license. This only allows people to download and share the work for no commercial gain and for no other purposes.
Licensing start date:23.05.2019

Secondary language

Language:English
Title:Logic gate simulator
Abstract:Due to the importance of the logic circuits, there are many different web and desktop applications available on the market today. They give the option to perform a simulation of their operation (e.g. Simulator.io, The logic Lab). Most of these applications are simulating outputs of the selected logic circuits, determined by the selected input values. Although this is understandable since multiple inputs into the logic circuit can be mapped to the same output, this type of simulation, which works only one-way, limits the possibilities of reverse engineering. In the thesis, we address this challenge by developing an algorithm that is able to analyze the selected logic circuit as well as evaluate the correct input values, at given output values. Our simulator enables a set of logic doors and sequential circuits. On this grounds, it evaluates the input values in order to get the desired results at the output. We performed various tests of the simulator through a combination of different output values options, in conjunction to the evaluation of the speed of it's operation.
Keywords:Logic gates, sequential circuit, reverse engineering, logic functions, algorithm


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