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Title:Integracija procesorskega jedra v NFC vmesnik : magistrsko delo
Authors:ID Slavinec, Kevin (Author)
ID Rojc, Matej (Mentor) More about this mentor... New window
ID Pleteršek, Anton (Co-mentor)
ID Bratuž, Iztok (Co-mentor)
Files:.pdf MAG_Slavinec_Kevin_2022.pdf (3,31 MB)
MD5: F23E591FC116B593C94E7936DDACE29F
Work type:Master's thesis/paper
Typology:2.09 - Master's Thesis
Organization:FERI - Faculty of Electrical Engineering and Computer Science
Abstract:V magistrski nalogi je opisana integracija in verifikacija procesorskega jedra v vmesnik NFC. Predstavljeno je osnovno delovanje posameznih sklopov integracije, delovanje vmesnika NFC in procesorskega jedra. Pri integraciji smo se soočili z načrtovanjem digitalnih blokov za medsebojno komunikacijo vmesnika NFC in procesorskega jedra preko podatkovnih vodil AHB in APB. Preuredili smo pomnilniško arhitekturo procesorskega jedra tako, da smo lahko postavili digitalni del – registre in notranji pomnilnik vmesnika NFC na mesta v pomnilniški arhitekturi, kjer dostopa procesorsko jedro. Za potrebe verifikacije sistema smo razvili programsko kodo za procesorsko jedro, preko katerega krmilimo vmesnik NFC. Delovanje vmesnika NFC smo preverili s simulacijo protokola FeliCa, s katerim smo simulirali prisotnost kartice na antenskih priključkih vmesnika NFC. S tem smo preverili sprejem in vpis podatkov v notranji pomnilnik vmesnika NFC. Soočili smo se tudi z načrtovanjem protokola SWD za razhroščevanje procesorskega jedra, vpisom programske kode preko SWD vodila v pomnilnik in izvajanje kode, vpisane v pomnilnik RAM.
Keywords:procesorsko jedro, vmesnik NFC, SoC, AHB, APB, FeliCa, SWD
Place of publishing:Maribor
Place of performance:Maribor
Publisher:[K. Slavinec]
Year of publishing:2022
Number of pages:1 spletni vir (1 datoteka PDF (XVII, 93 f.))
PID:20.500.12556/DKUM-82710 New window
COBISS.SI-ID:134619139 New window
Publication date in DKUM:21.10.2022
Categories:KTFMB - FERI
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License:CC BY-NC-ND 4.0, Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International
Description:The most restrictive Creative Commons license. This only allows people to download and share the work for no commercial gain and for no other purposes.
Licensing start date:30.08.2022

Secondary language

Title:Integration of processor core into NFC interface device
Abstract:This master thesis describes the integration and verification of a processor core with NFC interface. The basic operation of each integration unit, the operation of the NFC interface and processor core is presented. In the integration part, we designed digital blocks for communication between the NFC interface and processor core via AHB and APB data buses. We rearranged the memory architecture of the processor core for digital part of the NFC interface – the registers and the internal memory. In order to verify the system, we developed firmware for the processor, through which the NFC interface is controlled. We prepared a test bench for FeliCa protocol, which was used to simulate the presence of a card on the antenna pins of the SoC. With the successfully received packet in the processor core, we verified APB and AHB data bus connection between the processor core and NFC interface. We also made a test bench for the SWD protocol, which is used for debugging, loading program code into RAM, and executing the program code from RAM.
Keywords:Processor core, NFC interface, AHB, APB, FeliCa, SWD


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