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Title:Regulirana prožilna stopnja za močnostne tranzistorje
Authors:ID Horvat, Janko (Author)
ID Milanovič, Miro (Mentor) More about this mentor... New window
Files:.pdf EDOK_Horvat_Janko_2016.pdf (11,39 MB)
MD5: D1CD3529AD972DCA23284979A020DC60
 
Language:Slovenian
Work type:Dissertation
Typology:2.08 - Doctoral Dissertation
Organization:FERI - Faculty of Electrical Engineering and Computer Science
Abstract:V doktorski disertaciji je obravnavano področje proženja močnostnih tranzistorjev v strukturah stikalnih pretvornikov za trakcijske pogone osebnih vozil. Naloga prožilne stopnje je kontrolirano preklapljanje in zaščita močnostnih tranzistorjev pod vsemi pogoji uporabe ter kontrolirano doseganje varnega stanja pretvornika. Glede na študijo fizikalnih lastnosti močnostnih tranzistorjev in drugih za preklope relevantnih komponent stikalnega pretvornika so razviti napredni algoritmi in metode za prediktivno proženje, zaščito in opazovanje stanja močnostnega tranzistorja. Pri tem napredni algoritmi omogočajo brezsenzorsko ocenjevanje toka, temperature spoja in preostale življenjske dobe tranzistorja ter izbiro optimalnih strmin preklopov, kar omogoča zmanjšanje izgub, elektromagnetnih motenj in podaljša življenjsko dobo pretvornika. Na podlagi zahtev naprednih algoritmov in metod je razvita strojna oprema prožilne stopnje s PLD-vezjem, ki omogoča implementacijo in preizkušanje le-teh in nudi osnovo za razvoj regulirane prožilne stopnje za serijsko uporabo.
Keywords:močnostna elektronika, stikalni pretvornik, močnostni tranzistor, prožilna stopnja, opazovalnik, temperatura, toka, življenjska doba, elektromagnetne motnje, oblikovanje preklopa
Place of publishing:Maribor
Publisher:[J. Horvat]
Year of publishing:2016
PID:20.500.12556/DKUM-59705 New window
UDC:621.314.222.6:621.382.3(043.3)
COBISS.SI-ID:286226176 New window
NUK URN:URN:SI:UM:DK:INHV4QPM
Publication date in DKUM:07.07.2016
Views:1795
Downloads:221
Metadata:XML DC-XML DC-RDF
Categories:KTFMB - FERI
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Secondary language

Language:English
Title:Controlled gate driver for power transistors
Abstract:The thesis presents a gate driver stage with an advanced control algorithm for automotive traction power converters. The advanced control algorithm for predictive gate driving and protection is based on the study of semiconductor physics and other converter parts that influence the switching behavior. The advanced control algorithm incorporates a state observer to deliver sensorless junction temperature and phase current measurement, a lifetime consumption model, advanced switch protections and gate drive strength control to optimize electromagnetic noise and power losses. Also a gate driver hardware design based on a PLD and fast current sources is presented that enables the implementation of the developed control algorithm. The state observer is based on a simplified switch model and is built using two two-dimensional lookup tables. It is built as a direct model so measured characteristics can be used. The principle of operation is based on a sliding mode estimator with two inner loops estimating the switch current based on the plateau voltage and the on-state voltage drop across the switch. These two voltages are sampled corresponding during switching and on-state of the switch. The lifetime model is based on a Coffin-Manson lifetime model and uses temperature cycle detection for calculating life consumption. The junction temperature is derived from the state observer. As advanced protection a dynamic overcurrent protection is presented that enables switch protection / overcurrent detection during the switching event by monitoring the gate voltage. The expected plateau voltage is calculated by knowing the switch junction temperature and the expected switch current. The calculated plateau voltage is used to set a trip level for the gate voltage comparator. If the trip level is hit during switching an overcurrent event is detected and the switch is turned off safely. In addition switching times are monitored to detect abnormal switch behavior. Also a method for measuring the internal gate resistance of the semiconductor switch is presented. The principle of operation is by charging the gate with a known controlled current until a defined gate voltage is reached. Based on the measured time and gate capacitance the internal gate resistance is calculated. The advanced control algorithm also incorporates a gate drive strength control that enables voltage and/or current slope control during switching to optimize for overshoot at turn-off, EMC and power losses. The gate current is selected based on lookup tables and corrected by the estimated junction temperature and switch current. The thesis also present an experimental gate driver that enables testing of the presented methods. The gate driver is build using simple fast analog current sources witch are controlled by the FPGA. Fast feedback loops are implemented with three fast comparators for the gate voltage and the voltage across the switch. The trip level of the gate voltage comparator is controlled by the FPGA. Also two sample and hold units are implemented to allow event triggered gate voltage and on-state voltage measurement.
Keywords:: power electronics, converter, power transistor, gate driver, observer, temperature, current, lifetime, electromagnetic compatibility, switching waveform shaping


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