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Naslov:Izbira optimalnih podstruktur nerekurzivnega digitalnega sita v porazdeljeni aritmetiki
Avtorji:Solar, Mitja (Avtor)
Babič, Rudolf (Avtor)
Stiglic, Bruno (Avtor)
Datoteke:URL http://ev.fe.uni-lj.si/4-2003/solar.pdf
 
Jezik:Slovenski jezik
Vrsta gradiva:Neznano ()
Tipologija:1.01 - Izvirni znanstveni članek
Organizacija:FERI - Fakulteta za elektrotehniko, računalništvo in informatiko
Opis:Nerekurzivna digitalna sita v porazdeljeni aritmetiki in aritmetiki s fiksno decimalno vejico se uporabljajo v hitrih sistemih za digitalno obdelavo podatkov, kjer se zahteva stabilnost odzivov in linearne fazne poteke pri zahtevanem velikem dušenju ali veliki strmini bokov. Med različnimi realizacijskimi oblikami smo primerjali kaskadno, vzporedno in kombinirano realizacijsko obliko. Primerjali smo frekvenčne lastnosti, kvantizacijski šum in aparaturno kompleksnost.
Ključne besede:nerekurzivna digitalna sita, porazdeljena aritmetika, optimalne podstrukture, vplivi kvantizacije
Leto izida:2003
UDK:621.372.54
COBISS_ID:8492054 Povezava se odpre v novem oknu
ISSN pri članku:0013-5852
NUK URN:URN:SI:UM:DK:4P9O741J
Število ogledov:934
Število prenosov:19
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Gradivo je del revije

Naslov:Elektrotehniški vestnik
Založnik:Strokovna zadruga koncesijoniranih elektrotehnikov
ISSN:0013-5852
COBISS.SI-ID:742916 Novo okno

Sekundarni jezik

Jezik:Slovenski jezik
Naslov:Selection of an optimal substructure in the distributed arithmetic FIR digital filter
Opis:For digital signal processing in high-speed systems FIR digital filters are used, especially in applications where linear time-invariant stable response and linear phase are needed. A fixed point arithmetic is applied in such systems. The hardware main problem in the design of high-speed FIR digital filters is the complexity. In practical realizations of FIR digital filters, the circuits containe many adders, inverters, registers and multipliers. Among these basic digital elements, the multiplier has most of the hardware complexity and its time response is the greatest. A distributed arithmetic was developed for this reason by some authors. In the hardware realization the multiplier is substituted with a memory, adder and register. The partial sum of coefficients is written in the memory. The partial sum from memory with the previous result from the adder divided by two in the adder is calculated. The previous result from the adder is written in the register on b-iteration of the summed partial results is needed for the calculation of one entire product in the case of the distributed arithmetic. b is the number of bits in the input word. The complexity of the hardware realization of all FIR digital filters in the distributed arithmetic is determined with the word length in all substructures, with ripple in passband and stopband and with the width of transition band on the frequency response. With an increase in the word length, sharpness of the frequency response in transition band and reduction of ripple in passband and stopband the number of basic elements and the time response are increased. The capacity of the memory is determined with 2N, N is the number of impulse response coefficients. In modern digital filter designs the sampling frequency is limited to 20MHz and the number of impulse response coefficients to 200. With the new technology of digital circuits this limit will be increased. Our paper deals with the possibility of reducing the memory capacity by using a combined realization form. The combined realization form contains a cascade-connected structure built with a parallel subsection. We present two FIR digital filters in the distributed arithmetic realization form. The first one is realized with digital elements such as logic gates, adders, inverters and registers, and the other one with digital elements and read-write memory. Both forms are suitable for realization in custom-design integrated circuits or in PLD. Another advantage of our contribution is an optimal word length in all subsections with consideration of the roundoff noise and expected ripple in passband and stopband. As a result, an optimal lowpass FIR digital filter in the distributed arithmetic with 61 coefficients of the impulse response usefulness of the combined realization form is presented and analysed. For the combined realization form of the FIR digital filter design impulse response coefficients are needed. These coefficients can be calculated with software such as MATLAB. The impulseresponse coefficients h(k) are the coefficients of transfer function H(z). From the zeros of the transfer function of the FIR digital filter the zeros of the cascade structure are selected. This selection requires approximately an equal number of zeros in all cascaded structures, and a similar frequency response in all cascaded structures with the frequency response of the whole FIR digital filter. With this selection, the hardware complexity of the cascaded structure is almost the same and the magnitude of the output signal from all the cascaded structures is suitably high. The output signal as a response to the input white noise signal is calculated with our program package for simulation of an FIR digital filter structure. Depending on quantization errors, an optimal word length in all sections is chosen. The simulated results and the theoretically calculated quantization errors with linear quantization error models are compared. A simplified method for determination of the optimal word length was searched for by using theoretically calculated quant
Ključne besede:finite impulse response digital filters, distributed arithmetic, optimal substructure, quantization error analysis


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